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[IEEE Comput. Soc 5th International Symposium on Quality Electronic Design - San Jose, CA, USA (22-24 March 2004)] International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720) - Exact wiring fault minimization via comprehensive layout synthesis for CMOS logic cells

✍ Scribed by Iizuka, T.; Ikeda, M.; Asada, K.

Book ID: 126594756
Publisher: IEEE Comput. Soc
Year: 2004
Weight: 239 KB
Category: Article
ISBN-13: 9780769520933
DOI: 10.1109/ISQED.2004.1283703

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