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[IEEE Comput. Soc 5th International Symposium on Quality Electronic Design - San Jose, CA, USA (22-24 March 2004)] SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720) - Automated formal verification of scheduling process using finite state machines with datapath (FSMD)

✍ Scribed by Youngsik Kim, ; Kopuri, S.; Mansouri, N.

Book ID: 126476690
Publisher: IEEE Comput. Soc
Year: 2004
Tongue: English
Weight: 330 KB
Category: Article
ISBN-13: 9780769520933
DOI: 10.1109/ISQED.2004.1283659

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