The 87 papers in this proceedings of the January 2003 conference reflect the theme of convergence in system-on-a-chip design and the increasing need to design and verify hardware and software simultaneously. The collection explores on-going research in field programmable gate arrays, MOS technology,
[IEEE Comput. Soc 16th International Conference on VLSI Design. Concurrently with the 2nd International Conference on Embedded Systems Design - New Delhi, India (4-8 Jan. 2003)] 16th International Conference on VLSI Design, 2003. Proceedings. - Interconnect delay minimization using a novel pre-mid-post buffer strategy
โ Scribed by Prasad, V.; Desai, M.P.
- Book ID
- 118053966
- Publisher
- IEEE Comput. Soc
- Year
- 2003
- Weight
- 285 KB
- Volume
- 0
- Category
- Article
- ISBN-13
- 9780769518688
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The 87 papers in this proceedings of the January 2003 conference reflect the theme of convergence in system-on-a-chip design and the increasing need to design and verify hardware and software simultaneously. The collection explores on-going research in field programmable gate arrays, MOS technology,
The 87 papers in this proceedings of the January 2003 conference reflect the theme of convergence in system-on-a-chip design and the increasing need to design and verify hardware and software simultaneously. The collection explores on-going research in field programmable gate arrays, MOS technology,
The 87 papers in this proceedings of the January 2003 conference reflect the theme of convergence in system-on-a-chip design and the increasing need to design and verify hardware and software simultaneously. The collection explores on-going research in field programmable gate arrays, MOS technology,
The 87 papers in this proceedings of the January 2003 conference reflect the theme of convergence in system-on-a-chip design and the increasing need to design and verify hardware and software simultaneously. The collection explores on-going research in field programmable gate arrays, MOS technology,