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[IEEE Comput. Soc 14th Symposium on Computer Arithmetic - Adelaide, SA, Australia (14-16 April 1999)] Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) - Area×delay (A·T) efficient multiplier based on an intermediate hybrid signed-digit (HSD-1) representation

✍ Scribed by Lue, J.-J.J.; Phatak, D.S.

Book ID: 126725355
Publisher: IEEE Comput. Soc
Year: 1999
Weight: 195 KB
Category: Article
ISBN-13: 9780769501161
DOI: 10.1109/ARITH.1999.762847

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