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[IEEE 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Bangalore, India (2007.01.6-2007.01.10)] 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model

✍ Scribed by Wang, Feng; Xie, Yuan; Rajaraman, R.; Vaidyanathan, B.

Book ID: 118007609
Publisher: IEEE
Year: 2007
Weight: 404 KB
Volume: 0
Category: Article
ISBN-13: 9780769527628
DOI: 10.1109/vlsid.2007.145

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