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[IEEE 2014 15th International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2014.03.3-2014.03.5)] Fifteenth International Symposium on Quality Electronic Design - An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design

✍ Scribed by Uttraphan, C.; Shaikh-Husin, N.; Hani, M. Khalil

Book ID: 125451526
Publisher: IEEE
Year: 2014
Weight: 626 KB
Category: Article
ISBN: 1479939455
DOI: 10.1109/isqed.2014.6783348

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