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[IEEE 2014 15th International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2014.03.3-2014.03.5)] Fifteenth International Symposium on Quality Electronic Design - Minimizing clock domain crossing in Network on Chip interconnect

✍ Scribed by Kulkarni, Parag; Gupta, Puneet; Beraha, Rudy

Book ID: 125491056
Publisher: IEEE
Year: 2014
Weight: 327 KB
Category: Article
ISBN: 1479939455
DOI: 10.1109/ISQED.2014.6783339

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