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[IEEE 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) - Abu Dhabi (2013.3.26-2013.3.28)] 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) - Bottom-up design of a high performance ultra-low power DFT utilizing multiple-VDD, multiple-Vth and gate sizing

✍ Scribed by Jafari, M.; Imani, M.; Fathipour, M.; Sehatbakhsh, N.

Book ID: 121801964
Publisher: IEEE
Year: 2013
Weight: 239 KB
Category: Article
ISBN: 1467360384
DOI: 10.1109/DTIS.2013.6527804

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