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[IEEE 2008 3rd International Design and Test Workshop (IDT) - Monastir, Tunisia (2008.12.20-2008.12.22)] 2008 3rd International Design and Test Workshop - A novel fault tolerant design and an algorithm for tolerating faults in digital circuits

✍ Scribed by Kshirsagar, R.V.; Patrikar, R.M.

Book ID: 125813013
Publisher: IEEE
Year: 2008
Weight: 190 KB
Category: Article
ISBN: 1424434793
DOI: 10.1109/IDT.2008.4802486

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