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[IEEE 2007 IEEE International High Level Design Validation and Test Workshop - Irvine, CA, USA (2007.11.7-2007.11.9)] 2007 IEEE International High Level Design Validation and Test Workshop - An approach for computing the initial state for retimed synchronous sequential circuits

✍ Scribed by Chabini, Noureddine; Wolf, Wayne

Book ID: 121793438
Publisher: IEEE
Year: 2007
Weight: 637 KB
Category: Article
ISBN: 1424414806
DOI: 10.1109/HLDVT.2007.4392798

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