IC Compiler™ II Design Planning User Guide

✍ Scribed by Synopsys

• Year: 2016
• Tongue: English
• Leaves: 222
• Edition: Version L-2016.03-SP4
• Category: Library

✦ Table of Contents

Preface
Introduction to Design Planning
Design Planning Overview
Hierarchical Design Planning Flow
Design Partitioning
Deciding on the Physical Partitions
Design Planning at Multiple Levels of Physical Hierarchy
Splitting Constraints
Split Constraints Flow
Split Constraints Output Files
Split Constraints Example 1
Split Constraints Example 2
Running Tasks in Parallel
Monitoring Distributed Tasks
Creating a Floorplan
Supported Types of Floorplans
Channeled Floorplans
Abutted Floorplans
Narrow-Channel Floorplans
Reading the Verilog Netlist
Creating an Initial Floorplan
Creating an L-, T-, or U-Shaped Floorplan
Creating a Complex Rectilinear Floorplan
Adjusting the Floorplan Aspect Ratio
Flipping the First Row in the Floorplan
Updating the Floorplanning Without Disturbing Specified Object Types
Validating the FinFET Grid
Reporting Floorplan Information
Reading and Writing the Floorplan Information
Reading DEF Files
Writing the Floorplan and DEF Files
Handling Black Boxes
Identifying Potential Black Boxes
Creating Black Box References
Creating a Black Box Timing Model
Black Box Timing Example
Planning I/Os and Flip-Chip Bumps
Creating I/O Rings or Guides
Creating Arrays of Bump Cells
Placing Bump Cells in Predetermined Locations
Creating Power I/O Placement Constraints
Creating Signal I/O Placement Constraints
Assigning I/O Pads to Bumps With Matching Types
Placing I/Os and Writing Constraints
Routing RDL Nets
Optimizing RDL Routes
Creating RDL Net Shields
Managing Design Blocks
Exploring the Design Hierarchy
Creating Module Boundaries
Committing Design Blocks
Creating Block Placement Abstracts
Moving the Origin of a Block
Shaping Design Blocks and Macro Placement
Setting Macro Constraints
Creating Relative Placement Constraints for Macros and Macro Arrays
Setting Macro Keepouts
Shaping Blocks
Creating Block Shaping Constraints
Creating the Block Grid
Creating the Initial Macro Placement
Performing Power Planning
Creating and Connecting Power Nets
Defining PG Via Masters
Creating Power and Ground Ring Patterns
Creating Power and Ground Mesh Patterns
Creating Power and Ground Macro Connections
Creating Power and Ground Standard Cell Rails
Creating Channel and Alignment Power Straps
Creating Complex Composite Patterns
Creating Center-Aligned Vias
Creating Bridging Straps
Creating Via Bridging Straps
Creating Tapering Straps
Creating a Checkerboard Via Pattern
Defining Power Plan Regions
Setting the Power Plan Strategy
Strategy Settings for the -pattern Option
Strategy Settings for the -blockage Option
Strategy Settings for the -extension Option
Creating Via Rules Between Different Strategies
Instantiating the Power Plan
Pattern-Based Power Network Routing Example
Inserting and Connecting Power Switches
Setting Resistance Values for Power Switch Cells
Trimming the Power and Ground Mesh
Checking Power Network Connectivity and DRC
Checking Power Network Connectivity
Validating DRC in the Power Network
Performing Distributed Power Network Routing
Preparing for Distributed Power Network Routing
Performing Distributed Power Network Routing
Performing Global Planning
Creating Bundles and Bundle Constraints
Bundle Constraint Example
Creating Routing Corridors
Creating Global Routes Within Routing Corridors
Adding Repeater Cells
Pushing Down Repeater Cells
Performing Pin Assignment
Creating Global Pin Constraints
Creating Individual Pin Constraints
Reading Pin Constraints
Topological Map
Feedthrough Control
Physical Pin Constraints
Pin Spacing Control
Block Pin Constraints
Topological Constraint Examples
Creating a Direct Connection Between Blocks with Topological Constraints
Specifying a Partial Path
Performing Global Routing for Pin Placement
Creating a Channel Congestion Map
Placing Pins
Checking Pin Placement
Writing Pin Constraints
Writing Out Feedthroughs Inserted During Design Planning
Reporting Estimated Wire Length
Moving Objects Between the Top and Block Level
Performing Timing Budgeting
Creating Block Timing Abstracts
Performing Virtual In-Place Optimization
Applying Manual Budget Constraints
Updating Budget Information
Writing Out Budget Information