Design Compiler® User Guide

✍ Scribed by Synopsys

• Year: 2019
• Tongue: English
• Leaves: 792
• Edition: Version P-2019.03
• Category: Library

✦ Table of Contents

Preface
Design Compiler Introduction
About Design Compiler
Design Compiler NXT
Design Compiler Graphical
DC Ultra
DC Expert
The Design Compiler Family
About DC Explorer
About HDL Compiler
About Library Compiler
About Power Compiler
About DFT Compiler and DFTMAX
About Design Vision
Design Compiler in the Design Flow
High-Level Design Flow Tasks
Design Terminology
Designs
Design Objects
Design
Reference
Instance or Cell
Ports
Pins
Nets
Relationship Between Designs, Instances, and References
Selecting and Using a Compile Strategy
Optimization Basics
Working With Design Compiler
Running Design Compiler
Design Compiler Modes
Wire Load Mode (Default)
Topographical Mode
Multimode
UPF Mode
Working With Licenses
License Requirements
Enabling License Queuing
Listing the Licenses in Use
Checking Out Licenses
Checking DesignWare Licenses
Releasing Licenses
The Setup Files
Naming Rules Section of the .synopsys_dc.setup File
Starting the Tool in Wire Load Mode
Starting the Tool in Topographical Mode
Design Compiler Startup Tasks
Entering dcnxt_shell or dc_shell Commands
Redirecting the Output of Commands
Interrupting or Terminating Command Processing
Finding Session Information in the Log Files
Command Log Files
Compile Log Files
File Name Log Files
Using Script Files
Getting Help on the Command Line
Saving Designs and Exiting Design Compiler
The Synthesis Flow
A Design Compiler Session Example
Using Multicore Technology
Enabling Multicore Functionality
Measuring Runtime
Runtime Improvement Techniques Outside of Synthesis
Running Commands in the Background
Verification Guidance Support
Reporting Jobs Submitted To Run in the Background
Enabling Parallel Command Execution
Running Commands in Parallel in the Foreground
Supported Commands for Parallel Execution
Parallel Command Execution Design Flow
Preparing for Synthesis
Managing the Design Data
Controlling the Design Data
Organizing the Design Data
Partitioning for Synthesis
Partitioning for Design Reuse
Keeping Related Combinational Logic Together
Registering Block Outputs
Partitioning by Design Goal
Partitioning by Compile Technique
Keeping Sharable Resources Together
Keeping User-Defined Resources With the Logic They Drive
Isolating Special Functions
HDL Coding for Synthesis
Writing Technology-Independent HDL
Inferring Components
Using HDL Constructs
General HDL Constructs
Using Verilog Macro Definitions
Using VHDL Port Definitions
Writing Effective Code
Guidelines for Identifiers
Guidelines for Expressions
Guidelines for Functions
Guidelines for Modules
Instantiating RTL PG Pins
Performing Design Exploration
Creating Constraints
Setting Up and Working With Libraries
Selecting a Semiconductor Vendor
Library Requirements
Logic Libraries
Target Libraries
Link Libraries
Symbol Libraries
DesignWare Libraries
Physical Libraries
Specifying Logic Libraries
Specifying DesignWare Libraries
Specifying a Library Search Path
Setting Minimum Timing Libraries
Specifying Physical Libraries
Using TLUPlus Files for RC Estimation
Working With Libraries
Loading Libraries
Listing Libraries
Reporting Library Contents
Specifying Library Objects
Excluding Cells From the Target Libraries
Verifying Library Consistency
Removing Libraries From Memory
Saving Libraries
Target Library Subsets
Specifying Target Library Subsets
Setting Target Library Subset Examples
Checking Target Library Subsets
Reporting Target Library Subsets
Removing Target Library Subsets
Library Subsets for Sequential Cells and Instantiated Combinational Cells
Specifying the Library Cell Subsets
Reporting the Library Cell Subsets
Removing the Library Cell Subsets
Link Library Subsets
Specifying Link Library Subsets
Setting Link Library Subset Examples
Reporting Link Library Subsets
Removing Link Library Subsets
Library-Aware Mapping and Synthesis
Generating the ALIB File
Using the ALIB Library
Analyzing Multithreshold Voltage Library Cells
Handling Black Boxes
Supported Black Boxes
Black Box Flow
Defining Timing in Quick Timing Model Format
Defining Physical Dimensions
Estimating the Size of Black Boxes
Determining the Gate Equivalent Area
Identifying Black Box Cells
Automatic Creation of Physical Library Cells
Using a Milkyway Database
About the Milkyway Database
Required License and Files
Invoking the Milkyway Environment Tool
Guidelines for Using the Milkyway Database
Preparing to Use the Milkyway Database
Writing the Milkyway Database
Important Points About the write_milkyway Command
Limitations When Writing Milkyway Format
Working With Designs in Memory
Reading Designs
Supported Design Input Formats
Reading HDL Files
Reading Designs With Dependencies Automatically
Running the read_file Command
Running the analyze and elaborate Commands
Differences Between the read_file Command and the analyze and elaborate Commands
Running the read_verilog or read_vhdl Command
Reading .ddc Files
Reading .db Files
Listing Designs in Memory
Setting the Current Design
Linking Designs
How the Tool Resolves References
Locating Designs by Using a Search Path
Changing Design References
Querying Design References
Mapping Physical Variant Cells in Netlists or DEF Files
Listing Design Objects
Specifying Design Objects
Using a Relative Path
Using an Absolute Path
Using Attributes
Setting Attribute Values
Viewing Attribute Values
Saving Attribute Values
Defining Attributes
Propagating Attributes
Removing Attributes
The Object Search Order
Creating Designs
Copying Designs
Renaming Designs
Changing the Design Hierarchy
Adding Levels of Hierarchy
Removing Levels of Hierarchy
Ungrouping Hierarchies Before Optimization
Ungrouping Hierarchies Explicitly During Optimization
Ungrouping Hierarchies Automatically During Optimization
Preserving Hierarchical Pin Timing Constraints During Ungrouping
Merging Cells From Different Subdesigns
Editing Designs
Translating Designs From One Technology to Another
Translating Designs in Design Compiler Wire Load Mode
Translating Designs in Design Compiler Topographical Mode
Restrictions on Translating Between Technologies
Removing Designs From Memory
Saving Designs
Supported Design File Output Formats
Writing a Design Netlist or Schematic
Writing To a Milkyway Database
Saving Designs Using GUI Commands
Ensuring Name Consistency Between the Design Database and the Netlist
Specifying the Name Mapping and Replacement Rules
Resolving Naming Problems in the Flow
Avoiding Bit-Blasted Ports in SystemVerilog and VHDL Structures
Summary of Commands for Changing Names
Defining the Design Environment
Operating Conditions
Defining Operating Conditions
Reporting Operating Conditions
Modeling the System Interface
Defining Drive Characteristics for Input Ports
Defining Loads on Input and Output Ports
Defining Fanout Loads on Output Ports
Setting Logic Constraints on Ports
Allowing Assignment of Any Signal to an Input
Specifying Input Ports as Always One or Zero
Wire Load Models
Hierarchical Wire Load Models
Determining Available Wire Load Models
Specifying Wire Load Models and Modes
Defining the Environment Using Topographical Mode
General Gate-Level Power Optimization
Power Correlation
Multivoltage Designs
Low Power Intent
Multicorner-Multimode Designs
Leakage Power and Dynamic Power Optimization
Leakage Power Optimization Based on Threshold Voltage
Multithreshold Voltage Library Attributes
Setting Multithreshold Voltage Constraints
Leakage Optimization for Multicorner-Multimode Designs
Comparing Design Compiler Topographical and IC Compiler Environments
Comparing Design Settings Between Design Compiler and IC Compiler II
Defining Design Constraints
Constraint Types
Design Rule Constraints
Maximum Transition Time
Specifying Clock-Based Maximum Transition
Maximum Fanout
Maximum Fanout Calculation Example
Defining Maximum Fanout
Defining Expected Fanout for Output Ports
Maximum Capacitance
Specifying Frequency-Based Maximum Capacitance
Generating Maximum Capacitance Reports
Minimum Capacitance
Defining Minimum Capacitance
Cell Degradation
Connection Class
Summary of Design Rule Commands and Objects
Fixing Design Rule Violations
Disabling DRC Violation Fixing on Special Nets
Design Rule Constraint Precedence
Design Rule Scenarios
Optimization Constraints
Defining Timing Constraints
Maximum Delay
Minimum Delay
Defining Area Constraints (DC Expert Only)
Defining Power Constraints
Calculating Maximum Power Cost
Managing Constraint Priorities
Disabling the Cost Function
Reporting Constraints
Reporting Runtime Issues Related to SDC Constraints
Propagating Constraints in Hierarchical Designs
Characterizing Subdesigns
Using the characterize Command
Removing Previous Annotations
Optimizing Bottom Up Versus Optimizing Top Down
Deriving the Boundary Conditions
Saving Attributes and Constraints
The characterize Command Calculations
Characterizing Subdesign Port Signal Interfaces
Combinational Design Example
Sequential Design Example
Characterizing Subdesign Constraints
Characterizing Subdesign Logical Port Connections
Characterizing Multiple Instances
Characterizing Designs With Timing Exceptions
Limitations of the characterize Command
Propagating Constraints up the Hierarchy
Handling Conflicts Between Designs
Using Floorplan Physical Constraints
Importing Floorplan Information
Using the write_def Command in IC Compiler or IC Compiler II
Reading DEF Information in Design Compiler
Physical Constraints Imported in the DEF File
Extracting Physical-Only Cells From a DEF File
Macro and Port Name Matching With the extract_physical_constraints Command
Site Name Matching
Using the write_floorplan Command in IC Compiler
Reading the Floorplan Script in Design Compiler
Physical Constraints Imported in the Floorplan File
Macro and Port Name Matching With the read_floorplan Command
Reading and Writing Preroute Information for Power and Ground Nets and Physical-Only Cells
Manually Defined Physical Constraints
Defining Physical Constraints Overview
Defining the Die Area
Defining the Core Placement Area With the create_site_row Command
Defining Placement Area With the set_aspect_ratio and set_utilization Commands
Defining Port Locations
Defining Relative Port Locations
Defining Exact Port Locations
Defining Macro Location and Orientation
Defining Placement Blockages
Defining Voltage Areas
Defining Placement Bounds
Placement Bounds Overview
Creating Placement Bounds
Order for Creating Placement Bounds
Guidelines for Defining Placement Bounds Effectively
Returning a Collection of Bounds
Creating Wiring Keepouts
Creating Preroutes
Creating Preroutes for Power and Ground Nets
Creating User Shapes
Defining Physical Constraints for Pins
Creating Design Via Masters
Creating Vias
Creating Routing Tracks
Creating Keepout Margins
Computing Polygons
Including Physical-Only Cells
Specifying Physical-Only Cells Manually
Extracting Physical-Only Cells From a DEF File
Creating Collections With Physical-Only Cells
Reporting Physical-Only Cells
Saving Physical-Only Cells
Specifying Relative Placement
Relative Placement Overview
Benefits of Relative Placement
Methodology for the Relative Placement Flow
Relative Placement Flow Overview
Creating Relative Placement Using HDL Compiler Directives
Summary of Relative Placement Tcl Commands
Creating Relative Placement Groups
Anchoring Relative Placement Groups
Applying Compression to Relative Placement Groups
Specifying Alignment
Adding Objects to a Group
Querying Relative Placement Groups
Checking Relative Placement Constraints
Saving Relative Placement Information
Removing Relative Placement Group Attributes
Sample Script for a Relative Placement Flow
Magnet Placement
Resetting Physical Constraints
Saving Physical Constraints Using the write_floorplan Command
Saving Physical Constraints in IC Compiler Format
Saving Physical Constraints in IC Compiler II Format
Saving Physical Constraints Using the write_def Command
Reporting Physical Constraints
Reporting Routing Tracks
Reporting Preroutes
Reporting Design Via Masters
Reporting Keepout Margins
Compiling the Design
Compile Commands
The compile Command
The compile_ultra Command
Full and Incremental Compilation
Compile Strategies
Top-Down Compilation
Using the Top-Down Hierarchical Compile Strategy
Top-Down Hierarchical Compile Strategy Example
Bottom-Up Compilation
Using the Bottom-Up Hierarchical Compile Strategy
Bottom-Up Compile Script Example
Mixed Compile
Performing a Top-Level Compile
Using the -top Option With Other Compile Options
Limiting Optimization to Paths Within a Specific Range
Fixing Timing Violations For All Paths
Compile Log
Resolving Multiple Instances of a Design Reference
The Uniquify Method
Compile-Once-Don’t-Touch Method
Ungroup Method
Test-Ready Compile
Optimizing the Design
Overview of the Optimization Process
Architectural Optimization
Logic-Level Optimization
Gate-Level Optimization
Optimization Phases
Combinational Optimization
Technology-Independent Optimization
Mapping
Technology-Specific Optimization
Sequential Optimization
Initial Sequential Optimization
Final Sequential Optimization
Local Optimizations
Compile Cost Function
Optimization Flow
Automatic Ungrouping
High-Level Optimization and Datapath Optimization
Multiplexer Mapping and Optimization
Sequential Mapping
Structuring and Mapping
Automatic Uniquification
Implementing Synthetic Parts
Timing-Driven Combinational Optimization
Register Retiming
Delay and Leakage Optimization
Design Rule Fixing
Area Optimization
Optimization Techniques
Optimizing Once for Best- and Worst-Case Conditions
Constraint-Related Commands
Reporting Commands
Optimizing With Multiple Libraries
Preserving Subdesigns
Preserving Cells, References, and Designs
Preserving Nets
Removing a dont_touch Setting
Preserving the Clock Network After Clock Tree Synthesis
Optimizing Datapaths
Creating Path Groups
Controlling the Optimization of Your Design
Optimizing Near-Critical Paths
Optimizing All Paths
Controlling Automatic Path Group Creation
Controlling Path Group Weights During High-Effort Area Optimization
Isolating Input and Output Ports
Examples
Removing and Reporting Port Isolation Cells
Fixing Heavily Loaded Nets
Fixing Nets Connected to Multiple Ports
Optimizing Buffer Trees
Building Balanced Buffer Trees
Reporting Buffer Trees
Removing Buffer Trees
Optimizing Multibit Registers
Optimizing for Multiple Clocks Per Register
Example
Defining a Signal for Unattached Master Clocks
Example 1
Example 2
Optimizing Total Negative Slack During Placement
Optimizing Across Hierarchical Boundaries
Boundary Optimization
Disabling Boundary Optimization Throughout the Design
Disabling Boundary Optimization for a Specific Design
Controlling Constant Propagation
Controlling Constant Propagation When Boundary Optimization is Disabled
Disabling Constant Propagation Through Specific Hierarchical Pins
Controlling Phase Inversion
Propagating Unconnected Registers and Unconnected Bits of Multibit Registers Across Hierarchies With Boundary Optimization Disabled
Port Punching in Design Compiler Graphical
Port Punching and Phase Inversion With Automatic High-Fanout Synthesis
Other Optimizations That Affect Hierarchical Boundaries
Automatic Ungrouping
Automatic Ungrouping of Hierarchies
Automatic Ungrouping of Designs With Timing Exceptions
Exceptions to Automatic Ungrouping
High-Level Optimization and Datapath Optimization
Design Compiler Arithmetic Optimization
Synthetic Operators
High-Level Optimizations
Tree Delay Minimization and Arithmetic Simplifications
Resource Sharing
Common Subexpression Elimination
Sharing Mutually Exclusive Operations
Enhanced Resource Sharing
Datapath Optimization
Datapath Extraction
Datapath Implementation
Advanced Datapath Transformations
Analyzing Datapath Extraction
Reporting Resources and Datapath Blocks
Multiplexer Mapping and Optimization
Inferring SELECT_OPs
Inferring MUX_OPs
Library Cell Requirements for Multiplexer Optimization
Mapping Multiplexers on Asynchronous Signal Lines
Mapping to One-Hot Multiplexers
Inferring One-Hot Multiplexers
Library Requirements for One-Hot Multiplexers
Optimization of One-Hot Multiplexers
Sequential Mapping
Register Inference
Directing Register Mapping
Specifying the Default Flip-Flop or Latch
Specifying a Constant Value for Disabled Registers
Reporting Register Types
Reporting the Register Type Specifications for the Design
Reporting the Register Type Specifications for Cells
Unmapped Registers in a Compiled Design
Automatically Removing Unnecessary Registers
Removing Unconnected Registers
Eliminating Constant Registers
Controlling Constant Propagation Optimization
Constant Propagation Optimization for Complex Conditions
Merging Equal and Opposite Registers
Inverting the Output Phase of Sequential Elements
Mapping to Falling-Edge Flip-Flops
Resizing Black Box Registers
Preventing the Exchange of the Clock and Clock Enable Pin Connections
Mapping to Registers With Synchronous Reset or Preset Pins
Performing a Test-Ready Compile
Overview of Test-Ready Compile
Scan Replacement
Selecting a Scan Style
Mapping to Libraries Containing Only Scan Registers
Mapping to the Dedicated Scan-Out Pin
Automatic Identification of Shift Registers
Using Register Replication
Additional Register Replication Features in Topographical Mode
Adaptive Retiming
Comparing Adaptive Retiming With Pipelined-Logic Retiming
Adaptive Retiming Examples
Performing Adaptive Retiming
Controlling Adaptive Retiming
Reporting the dont_retime Attribute
Removing the dont_retime Attribute
Verifying Retimed Designs
Pipelined-Logic Retiming
Pipelined-Logic Retiming Overview
Pipelined-Logic Retiming Commands
Register Retiming Example
Register Retiming Concepts
Basic Definitions and Concepts
Flip-Flops and Registers
SEQGENs
Control Nets
Register Classes
Forward Retiming
Backward Retiming
Register Transformation Methods
Transforming Synchronous Input Pins Through Combinational Decomposition
Multiclass Retiming
Reset State Justification
Retiming the Design
Register Retiming Steps
Preventing Retiming
Selecting Transformation Options
Recommended Transformation Options for Pipelines
Recommended Transformation Options for Nonpipelines
Retiming Designs With Multiple Clocks
Retiming Registers With Path Group Constraints
Netlist Changes Performed by Register Retiming
Delay Threshold Optimization
Analyzing Retiming Results
Standard Output
Checking for Design Features That Limit the Quality of Results
Output Before Registers Are Moved
Output After Registers Are Moved
Displaying the Sequence of Cells That Limits Delay Optimization
Verifying Retimed Designs
Gate-Level Optimization
Delay Optimization
Power Optimization
Design Rule Fixing
Area Recovery
Using Topographical Technology
Overview of Topographical Technology
Inputs and Outputs in Design Compiler Topographical Mode
Defining the Design Environment
Performing Automatic High-Fanout Synthesis
Performing Manual High-Fanout Synthesis
Test Synthesis in Topographical Mode
Compile Flows in Topographical Mode
Performing an Incremental Compile
Performing a Bottom-up Hierarchical Compile
Overview of Bottom-Up Compile
Compiling the Subblock
Compiling the Design at the Top Level
Reducing Runtime
Handling Unsupported Commands, Options, and Variables
Using the Design Compiler Graphical Tool
Using Design Compiler Graphical
Using Synopsys Physical Guidance
Physical Guidance Overview
Reducing Routing Congestion
Routing Congestion Overview
Reducing Congestion in Highly Congested Designs
Enabling MUX Congestion Optimization
Optimizing High-Pin-Density Cells
Reducing Congestion in Incremental Compile
Reducing Congestion by Optimizing RTL Structures
Specifying Block-Level Congestion Optimization
Controlling Congestion Optimization
Reporting Congestion
Viewing Congestion With the Design Vision Layout Window
Congestion Map Calculations
Reducing Congestion in the Floorplan
Controlling Placement Density
Separating High-Pin-Density Cells
Allowing Cell Clusters
Improving Placement of Wide Cells
Clustering Logic Modules to Minimize QoR Variations
Specifying Design Constraints and Power Settings
Design-Specific Settings
Physical Constraints
Power Optimization Settings
Using Layer Optimization to Increase the Accuracy of Net Delay Estimation
Enabling Net Promotion to Multiple Layers
Working With Nondefault Routing Rules
Defining Nondefault Routing Rules
Applying Nondefault Routing Rules
Reporting Nondefault Routing Rules
Removing Nondefault Routing Rules
Managing Nondefault Routing Rules in the Design Flow
Automatic Assignment of Nondefault Routing Rules on Nets
Enabling the Physical Guidance Flow
Enabling the Physical Guidance Incremental Flow
Using Physical Guidance in IC Compiler
Using the Design Compiler Graphical and IC Compiler Hierarchical Flow
Improved Timing Correlation Between Design Compiler Graphical and IC Compiler II
Incremental ASCII Flow With a Third-Party DFT Flow Example
Exporting the Design
Saving in Binary Format
Saving in ASCII Format
Saving in ASCII Format for IC Compiler II
Reporting Physical Guidance Information
Physical Guidance Limitations
Floorplan Exploration Floorplanning With IC Compiler
Floorplan Exploration Overview
Enabling Floorplan Exploration
Running Floorplan Exploration
Using the Floorplan Exploration GUI
Creating and Editing Floorplans
Analyzing the Data Flow for Macro Placement
Saving the Floorplan or Discarding Updates
Saving the Floorplan into a Tcl Script File or DEF File
Exiting the Session
Incremental or Full Synthesis After Floorplan Changes
Using Floorplan Exploration With a dc_shell Script
Black Box Support
Handling Physical Hierarchies and Block Abstractions
Floorplan Exploration Floorplanning With IC Compiler II
License Requirements
Prerequisites for Floorplan Exploration
Command Summary
Running the Floorplan Exploration Flow
In Interactive Mode
In Batch Mode
Data Transfer to IC Compiler II
Working With Via Ladders
Reading In Via Ladders Defined in the Technology File
Creating, Querying, Removing, and Reporting Via Ladders
Performing What-If Analysis With Via Ladders
Performing Via-Ladder-Aware Optimization
Assigning of Via Ladders on Nets
Working With Must-Join Pins
Querying and Reporting the pattern_must_join Attribute
Checking the Inconsistency of pattern_must_join Attributes on Library Pins
Inbound Cell Optimization
Optimizing Multicorner-Multimode Designs
Multicorner-Multimode Concepts
Multicorner-Multimode Feature Support
Unsupported Features for Multicorner-Multimode Designs
Basic Multicorner-Multimode Flow
Creating a Scenario
Concurrent Multicorner-Multimode Optimization and Timing Analysis
Power Optimization in Multicorner-Multimode Designs
Setting Up the Design for a Multicorner-Multimode Flow
Specifying TLUPlus Files
Specifying Operating Conditions
Specifying Constraints
Handling Libraries in the Multicorner-Multimode Flow
Using Link Libraries That Have the Same PVT Nominal Values
Using Unique PVT Names to Prevent Linking Problems
Unsupported k-factors
Automatic Detection of Driving Cell Library
Defining Minimum Libraries
Scenario Management Commands
Creating Scenarios
Defining Active Scenarios
Scenario Reduction
Specifying Scenario Options
Removing Scenarios
Reporting Commands for Multicorner-Multimode Designs
report_scenarios Command
report_scenario_options Command
Reporting Commands That Support the -scenario Option
Commands That Report the Current Scenario
Reporting Examples
Supported SDC Commands for Multicorner-Multimode Designs
Multicorner-Multimode Script Example
Using Block Abstractions in Multicorner-Multimode Designs
Methodology for Using Block Abstractions With Scenarios at the Top Level
Using Design Compiler NXT
Performing Buffering-Aware Placement With the IC Compiler II Link
Performing Automatic Timing Control With the IC Compiler II Link
Performing Congestion-Driven Restructuring With the IC Compiler II Link
Performing RC Extraction With the RC Model
Applying Required Settings for High Performance Cores
Using Hierarchical Models
Overview of Hierarchical Models
Information Used in Hierarchical Models
Using Hierarchical Models in a Multicorner-Multimode Flow
Viewing Hierarchical Models in the GUI
Block Abstraction Hierarchical Flow
Creating and Saving Block Abstractions
Information Used in Block Abstractions
Block Abstractions for Multicorner-Multimode Usage
Setting Top-Level Implementation Options
Transparent Interface Optimization
Creating Block Abstractions for Nested Blocks
Resetting Implementation Options
Controlling the Extent of Logic Loaded for Block Abstractions
Loading Block Abstractions
Reporting Implementation Options
Reporting Block Abstractions
Reporting Block Abstraction Area
Querying Block Abstractions
Checking Block Abstractions
Ignoring Timing Paths That Are Entirely Within Block Abstractions
Performing Top-Level Synthesis
Saving Optimized Block Abstractions After Top-Level Synthesis
Limitations
Incremental ASCII Flow With a Third-Party DFT Flow Example
Performing Initial Compilation Using the compile.tcl Script
Performing Incremental Compilation Using the compile_incr.tcl Script
Using the Netlist SCANDEF Flow
Identifying the Scan Chain Structure
Performing Scan Chain Reordering in Design Compiler Graphical
Writing Out the New Scan Chain Structure
Analyzing and Resolving Design Problems
Resolving Bus Versus Bit-Blasted Mismatches Between the RTL and Macros
Fixing Errors Caused by New Unsupported Technology File Attributes
Using Register Replication to Solve Timing QoR, Congestion, and Fanout Problems
Assessing Design and Constraint Feasibility in Mapped Designs
Checking for Design Consistency
Checking Designs and Libraries Before Synthesis
Analyzing Your Design During Optimization Using the Compile Log
Analyzing Design Problems
Analyzing Area
Analyzing Timing
Reporting Quality of Results
Measuring Quality of Results
Analyzing Quality of Results
Displaying Quality of Results
Reporting Infeasible Paths
Reporting Infeasible Paths in an HTML Categorized Timing Report
Reporting Infeasible Paths in a Timing Report
Debugging Cells and Nets With dont_touch
Reporting dont_touch Cells and Nets
Creating a Collection of dont_touch Cells and Nets
Reporting size_only Cells
RTL Cross-Probing in the GUI
RTL Cross-Probing on the Command Line
Repeating RTL Cross-Probing
RTL Cross-Probing Report Example
Verifying Functional Equivalence
Setting Up SVF Generation
The guide_hier_map (GHM) Flow
The Formality Tool
Verification Guidance
Adjusting Optimization for Successful Verification
Using the set_verification_priority Command
Using Single-Pass Verification
Using Third-Party Formal Verification Tools
Design Example
Design Description
Setup File
Default Constraints File
Read Script
Compile Scripts
Basic Commands
Commands for Defining Design Rules
Commands for Defining Design Environments
Commands for Setting Design Constraints
Commands for Analyzing and Resolving Design Problems
Predefined Attributes
Latch-Based Design Code Examples
SR Latch
VHDL and Verilog Code Examples for SR Latch
Inference Report for an SR Latch
Synthesized Design for an SR Latch
D Latch
VHDL Code for a D Latch
Inference Report for a D Latch
Synthesized Design for a D Latch
D Latch With Asynchronous Reset
VHDL and Verilog Code for a D Latch With Asynchronous Reset
Inference Report for a D Latch With Asynchronous Reset
Synthesized Design for a D Latch With Asynchronous Reset
D Latch With Asynchronous Set and Reset
VHDL and Verilog Code for a D Latch With Asynchronous Set and Reset
Inference Report for a D Latch With Asynchronous Set and Reset
Synthesized Design for a D Latch With Asynchronous Set and Reset
D Latch With Enable (Avoiding Clock Gating)
VHDL and Verilog Code for a D Latch With Enable
Inference Report for a D Latch With Enable
Synthesized Design for a D Latch With Enable
Inferring Gated Clocks
Case 1
Case 2
Synthesized Design With Enable and Gated Clock
D Latch With Enable and Asynchronous Reset
VHDL and Verilog Code for a D Latch With Enable and Asynchronous Reset
Synthesized Design for a D Latch With Enable and Asynchronous Reset
D Latch With Enable and Asynchronous Set
VHDL and Verilog Code for a D Latch With Enable and Asynchronous Set
Synthesized Design for D Latch With Enable and Asynchronous Set
D Latch With Enable and Asynchronous Set and Reset
VHDL and Verilog Code for D Latch With Enable and Asynchronous Set and Reset
Synthesized Design for D Latch With Enable and Asynchronous Set and Reset