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Hybrid BIST energy minimisation technique for system-on-chip testing

✍ Scribed by Jervan, G.; Peng, Z.; Shchenova, T.; Ubar, R.

Book ID: 114448677
Publisher: The Institution of Electrical Engineers
Year: 2006
Tongue: English
Weight: 459 KB
Volume: 153
Category: Article
ISSN: 1350-2387
DOI: 10.1049/ip-cdt:20050064

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