✦ LIBER ✦

Hitachi launches RAM with 25 ns access time

Publisher: Elsevier Science
Year: 1985
Tongue: English
Weight: 91 KB
Volume: 9
Category: Article
ISSN: 0141-9331
DOI: 10.1016/0141-9331(85)90142-5

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

35 ns access with Inmos static RAM

📂 Article 📅 1983 🏛 Elsevier Science 🌐 English ⚖ 344 KB

Intel says static RAM has 35 ns access t

Intel says static RAM has 35 ns access time

📂 Article 📅 1984 🏛 Elsevier Science 🌐 English ⚖ 130 KB

A high speed 64 × 4 bit 100K-compatible

A high speed 64 × 4 bit 100K-compatible ECL-RAM with 6 NS access time: H. v. Witsch and H. Ernst. Fifth Solid Circuits Conference—ESSCIRC 79, IEE Publn.178, 102

📂 Article 📅 1980 🏛 Elsevier Science 🌐 English ⚖ 138 KB

A 7 ns 128K multichip ECL RAM-with-logic

A 7 ns 128K multichip ECL RAM-with-logic module: M Iwabuchi, K Ogiue, K Nakamura, S Makagami, S Isomura, S Kuroda, S Kawashima (Hitachi Device Dev. Center, Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 226–227, 411

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 91 KB

A 4-K byte/17-ns cache memory has been introduced to a 1.3 pm CMOS/bipolar macrocell library for VLSI computers. The memory includes an address translation function, which uses an MOS memory cell and a comparator merged with a bipolar sense amplifier to accelerate access time. (6 refs.)