High-speed low-power direct-coupled complementary push-pull ECL circuit

✍ Scribed by Chuang, C.T.; Chin, K.

• Book ID: 119774069
• Publisher: IEEE
• Year: 1994
• Tongue: English
• Weight: 359 KB
• Volume: 29
• Category: Article
• ISSN: 0018-9200
• DOI: 10.1109/4.303723

✦ Synopsis

This paper presents a high-speed low-power directcoupled complementary push-pull ECL (DC-PP-ECL) circuit. The circuit features a direct-coupled pnp pull-up and npn pulldown scheme with no extra biasing circuit for the push-and pulltransistor. The bias of the pull-up pnp transistor is established entirely by direct tapping of the existing voltage levels in the current switch. The scheme provides a sharp self-terminating dynamic current pulse through the pull-up pnp transistor during the switching transient, thus completely decoupling the collector load resistor from the delay path. Based on a 0.8-pm doublepoly self-aligned complementary bipolar process, the circuit offers 2.OX (2.2X) improvement in the loaded delay at 1.0 (0.5) mW/gate and 2.2X improvement in the load driving capability at 1.0 mW/gate compared with the conventional ECL circuit.