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A high-speed low-power JFET pull-down ECL circuit

โœ Scribed by Shin, H.J.; Lu, P.-F.; Chuang, C.-T.


Book ID
119775330
Publisher
IEEE
Year
1991
Tongue
English
Weight
530 KB
Volume
26
Category
Article
ISSN
0018-9200

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High-speed low-power direct-coupled comp
โœ Chuang, C.T.; Chin, K. ๐Ÿ“‚ Article ๐Ÿ“… 1994 ๐Ÿ› IEEE ๐ŸŒ English โš– 359 KB

This paper presents a high-speed low-power directcoupled complementary push-pull ECL (DC-PP-ECL) circuit. The circuit features a direct-coupled pnp pull-up and npn pulldown scheme with no extra biasing circuit for the push-and pulltransistor. The bias of the pull-up pnp transistor is established ent