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High-Performance Computing Using FPGAs || FPGA-Based Systolic Computational-Memory Array for Scalable Stencil Computations

✍ Scribed by Vanderbauwhede, Wim; Benkrid, Khaled


Book ID
120455838
Publisher
Springer New York
Year
2013
Tongue
English
Weight
998 KB
Edition
1st ed. 2013, Corr. 2nd printing 2014
Category
Article
ISBN
1461417910

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✦ Synopsis


High-Performance Computing using FPGA covers the area of high performance reconfigurable computing (HPRC). This book provides an overview of architectures, tools and applications for High-Performance Reconfigurable Computing (HPRC). FPGAs offer very high I/O bandwidth and fine-grained, custom and flexible parallelism and with the ever-increasing computational needs coupled with the frequency/power wall, the increasing maturity and capabilities of FPGAs, and the advent of multicore processors which has caused the acceptance of parallel computational models. The Part on architectures will introduce different FPGA-based HPC platforms: attached co-processor HPRC architectures such as the CHREC’s Novo-G and EPCC’sΒ  Maxwell systems; tightly coupled HRPC architectures, e.g. the Convey hybrid-core computer; reconfigurably networked HPRC architectures, e.g. the QPACE system, and standalone HPRC architectures such as EPFL’s CONFETTI system. The Part on Tools will focus on high-level programming approaches for HPRC, with chapters on C-to-Gate tools (such as Impulse-C, AutoESL, Handel-C, MORA-C ); Graphical tools (MATLAB-Simulink, NI LabVIEW); Domain-specific languages, languages for heterogeneous computing(for example OpenCL, Microsoft’s Kiwi and Alchemy projects).Β  The part on Applications will present case fromΒ  several application domains where HPRC has been used successfully, such as Bioinformatics and Computational Biology; Financial Computing; Stencil computations; Information retrieval; Lattice QCD; Astrophysics simulations; Weather and climate modeling.


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A linear systolic array of 256 cells for computing the Goldbach partitions has been designed and implemented on the FPGA PeRLe-1 platform. Fast computation is achieved using a counter based on a pseudo-random bit generator. Beyond this application we show that FPGA technology tends to promote such a