✦ LIBER ✦
An FPGA systolic array using pseudo-random bit generators for computing Goldbach partitions
✍ Scribed by Dominique Lavenier
- Publisher
- Elsevier Science
- Year
- 2000
- Tongue
- English
- Weight
- 302 KB
- Volume
- 30
- Category
- Article
- ISSN
- 0167-9260
No coin nor oath required. For personal study only.
✦ Synopsis
A linear systolic array of 256 cells for computing the Goldbach partitions has been designed and implemented on the FPGA PeRLe-1 platform. Fast computation is achieved using a counter based on a pseudo-random bit generator. Beyond this application we show that FPGA technology tends to promote such applications.