Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-
High-Level Verification: Methods and Tools for Verification of System-Level Designs
β Scribed by Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta (auth.)
- Publisher
- Springer-Verlag New York
- Year
- 2011
- Tongue
- English
- Leaves
- 182
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
β¦ Subjects
Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design
π SIMILAR VOLUMES
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