High-level test synthesis: a survey

✍ Scribed by Indradeep Ghosh; Niraj K Jha

• Book ID: 104305178
• Publisher: Elsevier Science
• Year: 1998
• Tongue: English
• Weight: 310 KB
• Volume: 26
• Category: Article
• ISSN: 0167-9260
• DOI: 10.1016/s0167-9260(98)00022-4

✦ Synopsis

This paper surveys the various high-level design for testability and synthesis for testability methods that have been proposed in the last decade. We begin with a description of high-level synthesis methods which target the ease of subsequent gate-level sequential test generation. Then we describe high-level synthesis methods which target built-in self-test (BIST) and hierarchical testability. Thereafter, we describe register-transfer level testability techniques that target gate-level test generation, BIST and hierarchical testability. We then describe some high-level test generation methods in brief.