Increases in the demand for integrated circuits have highlighted the importance of meeting customer quality and on-time delivery expectations in the semiconductor industry. A modiΓΏed shifting bottleneck heuristic is developed for minimizing the total weighted tardiness in a semiconductor wafer fabri
Heuristics for minimizing total weighted tardiness in complex job shops
β Scribed by Mason *, S.J.; Fowler, J.W.; Carlyle, W.M.; Montgomery, D.C.
- Book ID
- 126744643
- Publisher
- Taylor and Francis Group
- Year
- 2005
- Tongue
- English
- Weight
- 253 KB
- Volume
- 43
- Category
- Article
- ISSN
- 0020-7543
No coin nor oath required. For personal study only.
π SIMILAR VOLUMES
Consider a #exible #ow shop with s stages in series and at each stage a number of identical machines in parallel. There are n jobs to be processed and each job has to go through the stages following the same route. Job j has release date r H , due date d H , weight w H and a processing time p HJ at
We present a shifting bottleneck heuristic for minimizing the total weighted tardiness in a job shop. The method decomposes the job shop into a number of single-machine subproblems that are solved one after another. Each machine is scheduled according to the solution of its corresponding subproblem.