<p>HW/SW Co-Design for Heterogeneous Multi-Core Platforms describes the results and outcome of the FP6 project which focuses on the development of an integrated tool chain targeting a heterogeneous multi core platform comprising of a general purpose processor (ARM or powerPC), a DSP (the diopsis) an
Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain
โ Scribed by Koen Bertels (auth.), Koen Bertels (eds.)
- Publisher
- Springer Netherlands
- Year
- 2012
- Tongue
- English
- Leaves
- 254
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
โฆ Synopsis
HW/SW Co-Design for Heterogeneous Multi-Core Platforms describes the results and outcome of the FP6 project which focuses on the development of an integrated tool chain targeting a heterogeneous multi core platform comprising of a general purpose processor (ARM or powerPC), a DSP (the diopsis) and an FPGA. The tool chain takes existing source code and proposes transformations and mappings such that legacy code can easily be ported to a modern, multi-core platform. Downloadable software will be provided for simulation purposes.
โฆ Table of Contents
Front Matter....Pages I-XXII
Introduction....Pages 1-8
The hArtes Tool Chain....Pages 9-109
The hArtes Platform....Pages 111-123
Audio Array Processing for Telepresence....Pages 125-153
In Car Audio....Pages 155-192
Extensions of the hArtes Tool Chain....Pages 193-227
Conclusion: Multi-core Processor Architectures Are Here to Stay....Pages 229-231
โฆ Subjects
Circuits and Systems; Processor Architectures
๐ SIMILAR VOLUMES
<p>HW/SW Co-Design for Heterogeneous Multi-Core Platforms describes the results and outcome of the FP6 project which focuses on the development of an integrated tool chain targeting a heterogeneous multi core platform comprising of a general purpose processor (ARM or powerPC), a DSP (the diopsis) an
<p><P>System on Chip (SoC) platforms have become the de facto enabling technology for mobile multimedia personal communication and entertainment embedded systems. Among various architecture choices, application-specific instruction-set processors (ASIP) that incorporate sub-word parallelism provide
<p><P>System on Chip (SoC) platforms have become the de facto enabling technology for mobile multimedia personal communication and entertainment embedded systems. Among various architecture choices, application-specific instruction-set processors (ASIP) that incorporate sub-word parallelism provide
<p><P>System on Chip (SoC) platforms have become the de facto enabling technology for mobile multimedia personal communication and entertainment embedded systems. Among various architecture choices, application-specific instruction-set processors (ASIP) that incorporate sub-word parallelism provide
<p>Concurrent design, or co-design of hardware and software is extremely important for meeting design goals, such as high performance, that are the key to commercial competitiveness. <em>Hardware/Software Co-Design</em> covers many aspects of the subject, including methods and examples for designing