Automatic generation of command level si
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Hiroki Akaboshi; Hiroto Yasuura
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Article
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1996
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John Wiley and Sons
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English
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In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations.