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Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates

✍ Scribed by P. Corsonello; M. Lanuzza; S. Perri


Book ID
112071713
Publisher
John Wiley and Sons
Year
2012
Tongue
English
Weight
219 KB
Volume
42
Category
Article
ISSN
0098-9886

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