✦ LIBER ✦

Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates

✍ Scribed by P. Corsonello; M. Lanuzza; S. Perri

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Threshold voltage roll-up/roll-off chara

✍ Inaba, S.; Katsumata, R.; Akatsu, H.; Rengarajan, R.; Ronsheim, P.; Murthy, C.S. 📂 Article 📅 2002 🏛 IEEE 🌐 English ⚖ 156 KB