<i><p>System on Chip Interfaces for Low Power Design </i>provides a top-down understanding of interfaces available to SoC developers, not only the underlying protocols and architecture of each, but also how they interact and the tradeoffs involved. The book offers a common context to help understand
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
โ Scribed by Burg, Andreas; Edri, Noa; Fish, Alexander; Giterman, Robert; Meinerzhagen, Pascal; Teman, Adam
- Tongue
- English
- Leaves
- 151
- Category
- Library
No coin nor oath required. For personal study only.
โฆ Table of Contents
Front Matter....Pages i-ix
Embedded Memories: Introduction....Pages 1-12
Gain-Cell eDRAMs (GC-eDRAMs): Review of Basics and Prior Art....Pages 13-26
Retention Time Modeling: The Key to Low-Power GC-eDRAMs....Pages 27-48
Conventional GC-eDRAMs Scaled to Near-Threshold Voltage (NTV)....Pages 49-59
Novel Bitcells and Assist Techniques for NTV GC-eDRAMs....Pages 61-90
Aggressive Technology and Voltage Scaling (Down to the Subthreshold Domain)....Pages 91-111
Novel Bitcells for Scaled CMOS Nodes and Soft Error Tolerance....Pages 113-134
Conclusions....Pages 135-139
Back Matter....Pages 141-146
โฆ Subjects
Embedded computer systems;Systems on a chip;Integrated circuits -- Very large scale integration;COMPUTERS / General
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