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Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS

✍ Scribed by Narendra, S.; De, V.; Borkar, S.; Antoniadis, D.A.; Chandrakasan, A.P.

Book ID: 119799273
Publisher: IEEE
Year: 2004
Tongue: English
Weight: 913 KB
Volume: 39
Category: Article
ISSN: 0018-9200
DOI: 10.1109/jssc.2003.821776

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[IEEE Proceedings of the International Symposium on Low Power Electronics and Design - Monterey, CA, USA (2002.08.14-2002.08.14)] Proceedings of the International Symposium on Low Power Electronics and Design - Full-chip sub-threshold leakage power prediction model for sub-0.18 /spl mu/m CMOS

✍ Narendra, S.; De, V.; Borkar, S.; Antoniadis, D.; Chandrakasan, A. 📂 Article 📅 2002 🏛 IEEE ⚖ 420 KB