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[IEEE Proceedings of the International Symposium on Low Power Electronics and Design - Monterey, CA, USA (2002.08.14-2002.08.14)] Proceedings of the International Symposium on Low Power Electronics and Design - Full-chip sub-threshold leakage power prediction model for sub-0.18 /spl mu/m CMOS

✍ Scribed by Narendra, S.; De, V.; Borkar, S.; Antoniadis, D.; Chandrakasan, A.

Book ID: 126236348
Publisher: IEEE
Year: 2002
Weight: 420 KB
Category: Article
ISBN-13: 9781581134759
DOI: 10.1109/LPE.2002.146702

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