✦ LIBER ✦

Floorplanning for Partially Reconfigurable FPGAs

✍ Scribed by Banerjee, P.; Sangtani, M.; Sur-Kolay, S.

Book ID: 117908521
Publisher: IEEE
Year: 2011
Tongue: English
Weight: 653 KB
Volume: 30
Category: Article
ISSN: 0278-0070
DOI: 10.1109/tcad.2010.2079390

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Comparison of Preemption Schemes for Par

Comparison of Preemption Schemes for Partially Reconfigurable FPGAs

✍ Jozwik, K.; Tomiyama, H.; Edahiro, M.; Honda, S.; Takada, H. 📂 Article 📅 2012 🏛 Institute of Electrical and Electronics Engineers 🌐 English ⚖ 561 KB

Dynamic scheduling of tasks on partially

Dynamic scheduling of tasks on partially reconfigurable FPGAs

✍ Diessel, O.; ElGindy, H.; Middendorf, M.; Schmeck, H.; Schmidt, B. 📂 Article 📅 2000 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 306 KB

Floorplan Design for Multimillion Gate F

Floorplan Design for Multimillion Gate FPGAs

✍ Lei Cheng; Martin D. F. Wong 📂 Article 📅 2006 🏛 IEEE 🌐 English ⚖ 603 KB

A Partial Reconfiguration based Approach

A Partial Reconfiguration based Approach for Frequency Synthesis using FPGA

✍ Abhishek Tiwari 📂 Article 📅 2012 🏛 Elsevier 🌐 English ⚖ 429 KB

SiGe HBT BiCMOS FPGAs for fast reconfigu

SiGe HBT BiCMOS FPGAs for fast reconfigurable computing

✍ Goda, B.S.; McDonald, J.F.; Carlough, S.R.; Krawczyk, T.W., Jr.; Kraft, R.P. 📂 Article 📅 2000 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 185 KB

An Effective Framework to Evaluate Dynam

An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems

✍ Papadimitriou, K.; Anyfantis, A.; Dollas, A. 📂 Article 📅 2010 🏛 IEEE 🌐 English ⚖ 559 KB