Filter Design HDL Coder. User's Guide

• Publisher: MathWorks
• Year: 2023
• Tongue: English
• Leaves: 362
• Series: How to Contact MathWorks
• Category: Library

✦ Table of Contents

Getting Started
Filter Design HDL Coder Product Description
Key Features
Automated HDL Code Generation
Supported Filter System Objects
Basic FIR Filter
Create a Folder for Your Tutorial Files
Design a FIR Filter in Filter Designer
Quantize the Filter
Configure and Generate VHDL Code
Explore the Generated VHDL Code
Verify the Generated VHDL Code
Optimized FIR Filter
Create a Folder for Your Tutorial Files
Design the FIR Filter in Filter Designer
Quantize the FIR Filter
Configure and Generate Optimized Verilog Code
Explore the Optimized Generated Verilog Code
Verify the Generated Verilog Code
IIR Filter
Create a Folder for Your Tutorial Files
Design an IIR Filter in Filter Designer
Quantize the IIR Filter
Configure and Generate VHDL Code
Explore the Generated VHDL Code
Verify the Generated VHDL Code
HDL Filter Code Generation Fundamentals
Starting Filter Design HDL Coder
Opening the Filter Design HDL Coder UI from Filter Designer
Opening the Filter Design HDL Coder UI from the Filter Builder
Opening the Filter Design HDL Coder UI Using the fdhdltool Command
Selecting Target Language
Generating HDL Code
Applying Your Settings
Generating HDL Code from the UI
Generate HDL From the Command Prompt
Capturing Code Generation Settings
Closing Code Generation Session
Generate HDL Code for Filter System Objects
Using Filter Builder
Using Generate HDL
At the Command Line
HDL Code for Supported Filter Structures
Multirate Filters
Supported Multirate Filter Types
Generating Multirate Filter Code
Code Generation Options for Multirate Filters
Variable Rate CIC Filters
Supported Variable Rate CIC Filter Types
Code Generation Options for Variable Rate CIC Filters
Cascade Filters
Supported Cascade Filter Types
Generating Cascade Filter Code
Limitations for Code Generation with Cascade Filters
Polyphase Sample Rate Converters
Code Generation for Polyphase Sample Rate Converter
HDL Implementation for Polyphase Sample Rate Converter
Multirate Farrow Sample Rate Converters
Code Generation for Multirate Farrow Sample Rate Converters
Generating Code for dsp.FarrowRateConverter Filters at the Command Line
Generating Code for dsp.FarrowRateConverter Filters in the UI
Single-Rate Farrow Filters
Supported Single-Rate Farrow Filters
Code Generation Mechanics for Farrow Filters
Code Generation Properties for Farrow Filters
UI Options for Farrow Filters
Programmable Filter Coefficients for FIR Filters
UI Options for Programmable Coefficients
Generating a Test Bench for Programmable FIR Coefficients
Using Programmable Coefficients with Serial FIR Filter Architectures
Programmable Filter Coefficients for IIR Filters
Generate a Processor Interface for a Programmable IIR Filter
Generating a Test Bench for Programmable IIR Coefficients
Addressing Scheme for Loading IIR Coefficients
DUC and DDC System Objects
Limitations
Optimization of HDL Filter Code
Speed vs. Area Tradeoffs
Overview of Speed or Area Optimizations
Parallel and Serial Architectures
Specifying Speed vs. Area Tradeoffs via generatehdl Properties
Select Architectures in the Generate HDL Tool
Distributed Arithmetic for FIR Filters
Distributed Arithmetic Overview
Requirements and Considerations for Generating Distributed Arithmetic Code
Distributed Arithmetic via generatehdl Properties
Distributed Arithmetic Options in the Generate HDL Tool
Architecture Options for Cascaded Filters
CSD Optimizations for Coefficient Multipliers
Improving Filter Performance with Pipelining
Optimizing the Clock Rate with Pipeline Registers
Multiplier Input and Output Pipelining for FIR Filters
Optimizing Final Summation for FIR Filters
Specifying or Suppressing Registered Input and Output
Overall HDL Filter Code Optimization
Optimize for HDL
Set Error Margin for Test Bench
Customization of HDL Filter Code
HDL File Names and Locations
Setting the Location of Generated Files
Naming the Generated Files and Filter Entity
Set HDL File Name Extensions
Splitting Entity and Architecture Code Into Separate Files
HDL Identifiers and Comments
Specifying a Header Comment
Resolving Entity or Module Name Conflicts
Resolving HDL Reserved Word Conflicts
Setting the Postfix for VHDL Package Files
Specifying a Prefix for Filter Coefficients
Specifying a Postfix for Process Block Labels
Setting a Prefix for Component Instance Names
Setting a Prefix for Vector Names
Ports and Resets
Naming HDL Ports
Specifying the HDL Data Type for Data Ports
Selecting Asynchronous or Synchronous Reset Logic
Setting the Asserted Level for the Reset Input Signal
Suppressing Generation of Reset Logic
HDL Constructs
Representing VHDL Constants with Aggregates
Unrolling and Removing VHDL Loops
Using the VHDL rising_edge Function
Suppressing the Generation of VHDL Inline Configurations
Specifying VHDL Syntax for Concatenated Zeros
Specifying Input Type Treatment for Addition and Subtraction Operations
Suppressing Verilog Time Scale Directives
Using Complex Data and Coefficients
Verification of Generated HDL Filter Code
Testing with an HDL Test Bench
Workflow for Testing with an HDL Test Bench
Enabling Test Bench Generation
Renaming the Test Bench
Splitting Test Bench Code and Data into Separate Files
Configuring the Clock
Configuring Resets
Setting a Hold Time for Data Input Signals
Setting an Error Margin for Optimized Filter Code
Setting an Initial Value for Test Bench Inputs
Setting Test Bench Stimuli
Setting a Postfix for Reference Signal Names
Cosimulation of HDL Code with HDL Simulators
Generating HDL Cosimulation Blocks for Use with HDL Simulators
Generating a Simulink Model for Cosimulation with an HDL Simulator
Integration with Third-Party EDA Tools
Generate a Default Script
Customize Scripts for Compilation and Simulation
Synthesis and Workflow Automation
Automation Scripts for Third-Party Synthesis Tools
Select a Synthesis Tool
Customize Synthesis Script Generation
Programmatic Synthesis Automation
Filter Design HDL Coder Featured Examples
HDL Butterworth Filter
HDL Inverse Sinc Filter
HDL Minimum Phase FIRT Filter
HDL Tone Control Filter Bank
HDL Video Filter
HDL Digital Up-Converter (DUC)
HDL Fractional Delay (Farrow) Filter
HDL Sample Rate Conversion Using Farrow Filters
HDL Serial Architectures for FIR Filters
HDL Distributed Arithmetic for FIR Filters
HDL Programmable FIR Filter
Properties
Fundamental HDL Code Generation
HDL Filter Configuration
HDL Optimization
HDL Port and Identifier
HDL Construct
HDL Test Bench
HDL Synthesis and Workflow Automation
Functions
fdhdltool
generatehdl
generatetbstimulus
hdlfilterdainfo
hdlfilterserialinfo