𝔖 Scriptorium
✦   LIBER   ✦

πŸ“

DSP HDL Toolbox. User's Guide


Publisher
MathWorks
Year
2023
Tongue
English
Leaves
244
Category
Library

⬇  Acquire This Volume

No coin nor oath required. For personal study only.

✦ Table of Contents


Featured Examples
Align Parallel Data Streams
HDL Implementation of LMS Filter
High Performance DC Blocker for FPGA
Frequency-Domain Filtering in HDL
HDL Implementation of Four Channel Synthesizer and Channelizer
Gigasamples-per-Second Correlator and Peak Detector
NFC Digital Downconverter
Implement Digital Downconverter for FPGA
Implement Digital Upconverter for FPGA
HDL Optimized System Design
FIR Filter Architectures for FPGAs and ASICs
Complex Multipliers
Frame-Based Input Data
Fully Parallel Systolic Architecture
Fully Parallel Transposed Architecture
Partly Serial Systolic Architecture (1 < N < L)
Fully Serial Systolic Architecture (N β‰₯ L)
High-Throughput HDL Algorithms
Blocks that Support Frame-Based Input
Hardware Control Signals
Streaming Interface with Valid Signal
Backpressure Signal
Reset Signal
Block Reference Page Examples
Generate Sine Wave
Fully Parallel Systolic FIR Filter Implementation
Partly Serial Systolic FIR Filter Implementation
Optimize Programmable FIR Filter Resources
FIR Decimation for FPGA
Implement atan2 Function for HDL
Downsample a Signal
Control Data Rate Using Ready Signal
Automatic Delay Matching for the Latency of FFT Block
Implement CIC Interpolator Filter for HDL
Implement CIC Decimator Filter for HDL
Implement Downsampler For HDL
Implement Upsampler for HDL
Calculate Mean Square Error Performance Using LMS Filter
HDL Code Generation and Deployment
Prototype DSP HDL Algorithms on Hardware
How to Install Support Packages
Radar Application Examples
FPGA-Based Beamforming in Simulink: Algorithm Design
FPGA-Based Beamforming in Simulink: Code Generation
FPGA-Based Monopulse Technique: Algorithm Design
FPGA-Based Monopulse Technique: Code Generation
FPGA-Based Range-Doppler Processing - Algorithm Design and HDL Code Generation
FPGA-Based Cell-Averaging Constant False Alarm Rate (CA-CFAR) Detector
FPGA-Based Minimum-Variance Distortionless-Response (MVDR) Beamformer


πŸ“œ SIMILAR VOLUMES