Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing)

✍ Scribed by Fernanda Lima Kastensmidt, Ricardo Reis

Publisher: Springer
Year: 2006
Tongue: English
Leaves: 192
Edition: 1
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

This book reviews fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs), outlining many methods for designing fault tolerance systems. Some of these are based on new fault-tolerant architecture, and others on protecting the high-level hardware description before synthesis in the FPGA. The text helps the reader choose the best techniques project-by-project, and to compare fault tolerant techniques for programmable logic applications.

✦ Table of Contents

front-matter_1278......Page 1
1introduction_5549......Page 14
2radiation_effects_in_integrated_circuits_8606......Page 22
3single_event_upset__seu__mitigation_techniques_2078......Page 41
4architectural_seu_mitigation_techniques_5681......Page 84
5high-level_seu_mitigation_techniques_9586......Page 94
6triple_modular_redundancy__tmr__robustness_7031......Page 102
7designing_and_testing_a_tmr_micro-controller_1545......Page 122
8reducing_tmr_overheads_part_i_4590......Page 133
9reducing_tmr_overheads_part_ii_1662......Page 152
10final_remarks_1648......Page 180
back-matter_1286......Page 184

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