𝔖 Bobbio Scriptorium

✦ LIBER ✦

Fault-tolerance of cellular processing arrays: Algorithmic methods for yield enhancement and reliability

✍ Scribed by V.N. Doniants; V.G. Lazarev; R. Stefanelli

Publisher: Elsevier Science
Year: 1989
Weight: 466 KB
Volume: 25
Category: Article
ISSN: 0165-6074
DOI: 10.1016/0165-6074(89)90182-8

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Fault-tolerant ICs: the reliability of T

Fault-tolerant ICs: the reliability of TMR yield-enhanced ICs : Tim Haifley and Atul Bhatt. IEEE Trans. Reliab.R-36, 224 (1987)

📂 Article 📅 1989 🏛 Elsevier Science 🌐 English ⚖ 132 KB

Analysis technique for real-time, fault-

Analysis technique for real-time, fault-tolerant, VLSI processing arrays : ANDREW J. SCHWAB, BARRY W. JOHNSON and JOANNE BECHAT DUGAN. Proceedings of the Annual IEEE Reliability and Maintainability Symposium, 137 (1995)

📂 Article 📅 1996 🏛 Elsevier Science 🌐 English ⚖ 114 KB