✦ LIBER ✦

Fault characterization, testing considerations, and design for testability of BiCMOS logic circuits

✍ Scribed by Salama, A.E.; Elmasry, M.I.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Circuit testable design and universal te

✍ Zhongliang Pan 📂 Article 📅 2007 🏛 SP Science Press 🌐 English ⚖ 208 KB

On masking of redundant faults in synchr

✍ Pomeranz, I.; Reddy, S.M. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 338 KB

Testable design of two-dimensional cellu

✍ Bidyut Gupta; Bhargab B. Bhattacharya; Gopal C. Basu 📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 583 KB

Design of a logic circuit for microproce

✍ Ahmad, M.; Poornaiah, D. 📂 Article 📅 1987 🏛 IEEE ⚖ 484 KB

Role of test chips in coordinating logic

📂 Article 📅 1982 🏛 Elsevier Science 🌐 English ⚖ 123 KB

Characterization, test, and logic synthe

✍ Momenzadeh, M.; Jing Huang; Tahoori, M.B.; Lombardi, F. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 493 KB