✦ LIBER ✦

Experience using CAD for gate array design

✍ Scribed by Josef Kaiser

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Gate Arrays for VLSI Design

✍ Fulkerson, D. 📂 Article 📅 1982 🏛 IEEE 🌐 English ⚖ 618 KB

CAD-compatible high-speed CMOS/SIMOX gat

✍ Iwamatsu, T.; Yamaguchi, Y.; Inoue, Y.; Nishimura, T.; Tsubouchi, N. 📂 Article 📅 1995 🏛 IEEE 🌐 English ⚖ 539 KB

Microcontroller compatible clock chip de

✍ Noore, A. 📂 Article 📅 1991 🏛 IEEE 🌐 English ⚖ 605 KB

Logical launches design service for gate

📂 Article 📅 1987 🏛 Elsevier Science 🌐 English ⚖ 131 KB

Two CMOS gate arrays for the EPACT exper

✍ Winkert, G. 📂 Article 📅 1992 🏛 IEEE 🌐 English ⚖ 557 KB

Test Engineering for CMOS Gate Arrays wi

✍ Scherer, Olaf 📂 Article 📅 1986 🏛 IEEE 🌐 English ⚖ 998 KB