Emerging Technologiesand Circuits
Foreword
Contents
Part I:Introduction
Synergy Between Design and Technology: A Key Factor in the Evolving Microelectronic Landscape
1 Introduction
2 Classical Scaling
2.1 Lithography
2.2 Interconnections
2.3 Yield Enhancement
3 Equivalent Scaling
4 Integrated Solutions
5 Emerging Research Devices and Architectures
5.1 Bottom-Up Approach
5.2 Top-Down Approach
5.3 Morphic´´ Systems
6 What Business Model?
7 Conclusion
References
Part II:Emerging Technologies and Circuits
New State Variable Opportunities Beyond CMOS: A System Perspective
1 Introduction
2 System Capability
3 Alternate Device Options
4 Device and Interconnect Abstractions
4.1 Device Scaling Physical Limits
4.2 Device Density: Tiling Considerations
4.3 Minimum Device Switching Time
4.4 Energy Per Bit Operation
4.5 Interconnect Costs for Electronic Circuits
4.6 Fan-Out Costs
4.7 Energy Per Tile
4.8 Digital Circuit Abstraction
5 Energy/Performance Analysis of a Minimal Turing Machine
5.1 Minimum Instruction Set 1-Bit Arithmetic Logic Unit
5.2 Energetics of the Minimal ALU
5.3 Minimal ALU Timing
5.4 Minimal Turing Machine: Device Count
5.5 Minimal Turing Machine: A Numerical Summary
6 Conclusions
References
A Simple Compact Model to Analyze the Impact of Ballistic and Quasi-Ballistic Transport on Ring Oscillator Performance
1 Introduction
2 Analytical Model
2.1 Backscattering View
2.2 Drain Current Modeling
3 Simulation and Discussion
3.1 Ballistic and Quasi-Ballistic Transport
3.2 Circuit Level Simulations
3.3 Impact of Quasi-Ballistic Transport on Circuit Performances
4 Conclusion
References
Part III:Advanced Devices and Circuits
Low-Voltage Scaled 6T FinFET SRAM Cells
1 Introduction
2 Device Fabrication
3 Results and Discussion
3.1 Ring Oscillators
3.2 SRAM Performance
3.3 Device and SRAM Variability
4 Conclusions
References
Independent-Double-Gate FINFET SRAM Cell for Drastic Leakage Current Reduction
1 Introduction
2 Fabrication Procedure
3 Results and Discussons
3.1 Fabrication Results
3.2 CMOS Inverter Operation
3.3 SRAM Operations
4 Conclusion
References
Metal Gate Effects on a 32 nm Metal Gate Resistor
1 System - On - Chip Requirements
2 High-K/Metal Gate Effects on Passives
3 P+ A-Silicon/Metal Resistor
4 Summary
References
Part IV:Reliability and SEU
Threshold Voltage Shift Instability Induced by Plasma Charging Damage in MOSFETS with High-K Dielectric
1 Introduction
2 Experimental
3 Results and Discussion
3.1 Gate Leakage Characteristics
3.2 MOSFETs Characteristics
3.3 Mechanisms of Charging Polarity and Vt Shift Instability
3.4 Impacts on Damage Characterization of High-k Devices
4 Conclusion
References
Analysis of SI Substrate Damage Induced by Inductively Coupled Plasma Reactor with Various Superposed Bias Frequencies
1 Introduction
2 Experimental
2.1 Plasma Exposure with Superposed Bias Frequencies
2.2 Spectroscopic Ellipsometry
2.3 Photoreflectance Spectroscopy
2.4 Current-Voltage Measurement
3 Results and Discussion
3.1 SE and PR analyses
3.2 C-V Analysis
4 Conclusion
References
Part V:Power, Timing and Variability
CMOS SOI Technology for WPAN: Application to 60 GHZ LNA
1 Introduction
2 Modeling SOI CMOS 65NM Technology
3 Low Noise Amplifiers in 65-NM SOI CMOS
4 Conclusion
References
SRAM Memory Cell Leakage Reduction Design Techniques in 65 nm Low Power PD-SOI CMOS
1 Introduction
2 Design Leakage Reduction Techniques
3 Cell Stability Versus Leakage Strategy
4 Results
5 Conclusion
References
Resilient Circuits for Dynamic Variation Tolerance
1 Introduction
2 Error-Detection Sequential Circuits
2.1 Overview
2.2 Razor I
2.3 Transition Detector with Time Borrowing (TDTB)
2.4 Double Sampling with Time Borrowing (DSTB)
2.5 Razor II
2.6 Advantages and Disadvantages
3 Error-Recovery Circuits
3.1 Counter-Flow Pipeline Error Recovery
3.2 Instruction-Replay Error Recovery
3.3 Clock Divider and Duty-Cycle Control Circuits
4 Resilient Circuit Measurements
4.1 Resilient Circuit Demonstration
4.2 Resilient Circuit Performance and Power Benefits
5 Conclusion
References
Process Variability-Induced Timing Failures - A Challenge in Nanometer CMOS Low-Power Design
1 Introduction
2 Effects of Process Variability on Timing
2.1 Path Delay Variation
2.2 Delay Variation Voltage Dependency
2.3 Delay Variation Transistor Size Dependency
2.4 Delay Variation Stage Dependency
2.5 Timing Skew Due to Process Variability
3 New Timing Failure at Low Voltage and Its Characteristics
4 Variability-Resilient Design Methodology
5 Challenge in Low-Power Designs
6 Conclusion
References
How Does Inverse Temperature Dependence Affect Timing Sign-Off
1 Introduction
2 Experimental Study
2.1 Temperature Versus Delay Relationship
2.2 Impact of VTH
2.3 Impact of Supply Voltage
2.4 Impact of Process Variation
2.5 Random Cells and Loading
2.6 ITD Impact on Path
3 Potential Solution
4 Conclusion
References
CMOS Logic Gates Leakage Modeling Under Statistical Process Variations
1 Introduction
2 Analytical Model of Current Leakage Under Process Variations
2.1 Mathematical Problem Formulation
2.2 Leakage Distribution of a Single Transistor
2.3 Leakage Distribution of Logic Gates
3 Results
4 Conclusions
References
On-Chip Circuit Technique for Measuring Jitter and Skew with Picosecond Resolution
1 Jitter and Skew in VLSI Circuits
2 Circuit Design
3 Jitter Measurement with On-Chip Circuit
3.1 Jitter Definitions
3.2 Long-Term Jitter
3.3 Period Jitter
4 Clock Skew Measurement with On-Chip Circuit
5 Summary
References
Part VI:Analog and Mixed Signal
DC-DC Converter Technologies for On-Chip Distributed Power Supply Systems - 3D Stacking and Hybrid Operation
1 Introduction
2 3D-Structured Buck Converter
2.1 Theoretical Analysis of Power Efficiency
2.2 Si-CMOS + Si-CMOS Implementation
2.3 Si-CMOS + Interposer Implementation
2.4 W-CSP Implementation
3 Hybrid Operation of Linear Regulator and Buck Converter
3.1 Quick Wake-Up and Power Gating
3.2 Measured Results
4 Conclusions
References
Sampled Analog Signal Processing: From Software-Defined to Software Radio
1 The Software Radio Concept
1.1 Introduction
1.2 Definition and History
1.3 Technological Bottlenecks Constrained by Mobile Context
2 Digital Software Defined Radio Receiver
2.1 Heterodyne Front-End Receiver Architecture with IF A/D Conversion -Digital Receiver´´
2.2 Digital Receiver Using Band Pass Delta-Sigma A/D Converter
2.3 Proposed Continuous-Time Band Pass Delta-Sigma Modulator
3 A Disruptive Software Radio Receiver Architecture
3.1 Sampled Analog Signal Processor
3.1.1 Principle
3.1.2 A Fast Fourier Transform
3.2 Architecture
3.2.1 A Pipelined Analog FFT
3.2.2 Design Matters
3.2.3 A 64-Sample SASP
3.3 A Software Radio System
3.3.1 SASP Configuration
3.3.2 Frequency Demodulation
3.3.3 Concurrent Reception
4 Conclusion
References