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Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder

✍ Scribed by Johnson, B.W.; Aylor, J.H.; Hana, H.H.

Book ID: 118138221
Publisher: IEEE
Year: 1988
Tongue: English
Weight: 768 KB
Volume: 23
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.281

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