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Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's)

✍ Scribed by Kobayashi, F.; Haratsu, M.; Yabumoto, M.; Nakano, M.


Book ID
119776549
Publisher
IEEE
Year
1996
Tongue
English
Weight
464 KB
Volume
43
Category
Article
ISSN
1932-4529

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## Abstract A low‐cost, compact, high‐performance clock‐recovery (CR) module using a new phase‐locked loop (PLL) for 40‐Gb/s optical receivers is successfully designed and implemented. The newly implemented frequency detector in the PLL helps to reduce the current consumption and also extended the