The development of computing machines found great success in the last decades. But the ongoing miniaturization of integrated circuits will reach its limits in the near future. Shrinking transistor sizes and power dissipation are the major barriers in the development of smaller and more powerful circ
β¦ LIBER β¦
Efficient debugging in a formal verification environment
β Scribed by Fady Copty; Amitai Irron; Osnat Weissberg; Nathan Kropp; Gila Kamhi
- Book ID
- 106245341
- Publisher
- Springer
- Year
- 2003
- Tongue
- English
- Weight
- 516 KB
- Volume
- 4
- Category
- Article
- ISSN
- 1433-2779
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The use of a formal synthesis system is proposed as an efficient alternative for the formal verification of RT-level circuits obtained from algorithmic-level specifications by high-level synthesis (HLS) tools. The goal of the proposal is to recreate, within the formal synthesis system, any design pr