✦ LIBER ✦

Device simulations for low voltage/low power silicon CMOS device design

✍ Scribed by Srinivas Jallepalli; Mahbub Rashed; Peter Zdebel

Publisher: Elsevier Science
Year: 1997
Tongue: English
Weight: 394 KB
Volume: 39
Category: Article
ISSN: 0167-9317
DOI: 10.1016/s0167-9317(97)00171-8

No coin nor oath required. For personal study only.

✦ Synopsis

Device simulations are becoming an increasingly attractive alternative to traditional, experiment-based technology development. This is due to the sky-rocketing development costs, increasing process complexity and finally the increasing maturity of the device simulation tools. In this chapter, we discuss some of the issues involved in low power CMOS device design using fulbfledged (two-dimensional) numerical device simulations. The roles played by vertical channel profile engineering, the halo/pocket implants and shallow source / drain extensions in minimizing short channel effects is discussed.

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