Design-performance trade-offs in CMOS-domino logic

Trade-offs in linear filter design

✍ G.C. Goodwin; D.Q. Mayne; J. Shim 📂 Article 📅 1995 🏛 Elsevier Science 🌐 English ⚖ 923 KB

Performance limitations in filtering are investigated, and it is shown that some of these are fundamental and independent of design method.

Impact of NBTI on performance of domino

Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

✍ M. Houshmand Kaffashian; R. Lotfi; K. Mafinezhad; H. Mahmoodi 📂 Article 📅 2011 🏛 Elsevier Science 🌐 English ⚖ 466 KB

Multi-Voltage CMOS Circuit Design (Kursu

Multi-Voltage CMOS Circuit Design (Kursun/Multi-Voltage CMOS Circuit Design) || Sleep Switch Dual Threshold Voltage Domino Logic

✍ Kursun, Volkan; Friedman, Eby G. 📂 Article 📅 2006 🏛 John Wiley & Sons, Ltd 🌐 English ⚖ 449 KB

This book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages. A detailed discussion of the sources of power consumption in CMOS circuits will be provided whilst focusing primarily on identifying the mechanisms by

Multi-Voltage CMOS Circuit Design (Kursu

Multi-Voltage CMOS Circuit Design (Kursun/Multi-Voltage CMOS Circuit Design) || Domino Logic with Variable Threshold Voltage Keeper

✍ Kursun, Volkan; Friedman, Eby G. 📂 Article 📅 2006 🏛 John Wiley & Sons, Ltd 🌐 English ⚖ 492 KB

This book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages. A detailed discussion of the sources of power consumption in CMOS circuits will be provided whilst focusing primarily on identifying the mechanisms by

Charge redistribution and noise margins

Charge redistribution and noise margins in domino CMOS logic

✍ Pretorius, J.; Shubat, A.; Salama, C. 📂 Article 📅 1986 🏛 IEEE ⚖ 892 KB

Testing for multiple faults in domino-CM

Testing for multiple faults in domino-CMOS logic circuits

✍ Jha, N.K. 📂 Article 📅 1988 🏛 IEEE 🌐 English ⚖ 921 KB