✦ LIBER ✦

Design of synchronous and asynchronous variable-latency pipelined multipliers

✍ Scribed by Olivieri, M.

Book ID: 118132262
Publisher: IEEE
Year: 2001
Tongue: English
Weight: 337 KB
Volume: 9
Category: Article
ISSN: 1063-8210
DOI: 10.1109/92.924058

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Design of power-efficient pipelined trun

Design of power-efficient pipelined truncated multipliers with various output precision

✍ S.-R. Kuang; J.-P. Wang 📂 Article 📅 2007 🏛 The Institution of Engineering and Technology 🌐 English ⚖ 328 KB

Synchronous and asynchronous presentatio

Synchronous and asynchronous presentations of auditory and visual signals: Implications for control console design

✍ Alan H.S. Chan; Ken W.L. Chan 📂 Article 📅 2006 🏛 Elsevier Science 🌐 English ⚖ 276 KB

Design and functional tests of variable

Design and functional tests of variable SFQ pulse number multiplier

✍ J. Saito; T. Tanaka; M. Moriya; T. Kobayashi; Y. Mizugaki; M. Maezawa 📂 Article 📅 2011 🏛 Elsevier Science 🌐 English ⚖ 779 KB

Improving power-awareness of pipelined a

Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design

✍ Jia Di; J.S. Yuan; R. Demara 📂 Article 📅 2006 🏛 Elsevier Science 🌐 English ⚖ 394 KB

Design and evaluation of variable stages

Design and evaluation of variable stages pipeline processor with low-energy techniques

✍ Nakabayashi, T.; Sasaki, T.; Ohno, K.; Kondo, T. 📂 Article 📅 2012 🏛 The Institution of Engineering and Technology 🌐 English ⚖ 646 KB

Design and characterisation of a CMOS VL

Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure

✍ Acosta, A.J.; Jimenez, R.; Barriga, A.; Bellido, M.J.; Valencia, M.; Huertas, J. 📂 Article 📅 1998 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 743 KB