✦ LIBER ✦
Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure
✍ Scribed by Acosta, A.J.; Jimenez, R.; Barriga, A.; Bellido, M.J.; Valencia, M.; Huertas, J.L.
- Book ID
- 114447670
- Publisher
- The Institution of Electrical Engineers
- Year
- 1998
- Tongue
- English
- Weight
- 743 KB
- Volume
- 145
- Category
- Article
- ISSN
- 1350-2409
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