Design of New Optimized Architecture Processor for DWT

✍ Scribed by Chokri Souani; Mohamed Atri; Mohamed Abid; Kholdoun Torki; Rached Tourki

• Publisher: Elsevier Science
• Year: 2000
• Tongue: English
• Weight: 821 KB
• Volume: 6
• Category: Article
• ISSN: 1077-2014
• DOI: 10.1006/rtim.1999.0178

✦ Synopsis

his paper presents a VLSI implementation of One Dimensional Direct Discrete Wavelet transform (1-D DWT). The DDWT can be viewed as a multi-resolution decomposition of a signal. This means that it decomposes a signal into its components in dierent frequency bands (octave bands). We propose a new architecture using parallel ®lters. We consider the implementation of 1-D three levels DWT. The proposed architecture is simple and oers 16-bit precision on input and output data. It is constituted of three basic units: one register bank, four ®lters, and a control unit. The ®lters are of dierent lengths and with new coecients derived from Daubechies ®lter coecients. The designed processor architecture requires no interface circuitry for interconnection to a standard communication bus. The architecture can compute DWT at a data rate of 12 x 10 6 samples/s corresponding to a typical clock speed of 12 MHz. The architecture is simulated at the gate level in VLSI.