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Design of multipliers for GF(2m)

โœ Scribed by Mao, Z.; Shou, G.; Hu, Y.; Guo, Z.


Book ID
121249954
Publisher
The Institution of Electrical Engineers
Year
2010
Tongue
English
Weight
107 KB
Volume
46
Category
Article
ISSN
0013-5194

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This paper presents a new digit-serial systolic multiplier over GF (2 m ) for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every m/D + 2 clock cycles, where D is the selected digit size. Since the inner structur