Design of a digitally controlled oscillator for a Delta-Sigma phase-locked loop in a 0.13 µm CMOS-process

Using CAD tools for shortening the desig

Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology

✍ Medeiro, Fernando; Pérez-Verdú, Belén; De La Rosa, José M.; Rodríguez-Vázquez, Á 📂 Article 📅 1997 🏛 John Wiley and Sons 🌐 English ⚖ 375 KB 👁 1 views

This paper uses a CAD methodology proposed by the authors to design a low-power second-order M. This modulator has been fabricated in a 0•7 m CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16•4 bit at a digital output rate of 9•6 kHz with a power con