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Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes

✍ Scribed by Chen, J.Z.; Amerasekera, E.A.; Duvvury, C.

Book ID
114537495
Publisher
IEEE
Year
1998
Tongue
English
Weight
510 KB
Volume
45
Category
Article
ISSN
0018-9383

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