Design and implementation of a miniaturized high-linearity 3–5 GHz ultrawideband CMOS low-noise amplifier

✍ Scribed by Yo-Sheng Lin; Zheng-Hua Yang; Chi-Chen Chen; Tai-Cheng Chao

• Publisher: John Wiley and Sons
• Year: 2007
• Tongue: English
• Weight: 325 KB
• Volume: 49
• Category: Article
• ISSN: 0895-2477
• DOI: 10.1002/mop.22175

✦ Synopsis

Abstract

In this article, we demonstrate a miniaturized high‐linearity (IIP3 = 8 dBm at 4 GHz) 3–5‐GHz ultrawideband low‐noise amplifier (LNA) implemented in a standard 0.18‐μm CMOS technology. The inductive‐series peaking technique was used to enhance the gain and bandwidth performances of the LNA. The measurement results show voltage gain greater than 10 dB, reverse isolation (S~12~) lower than −15 dB, and noise figure lower than 3.3 dB were achieved for frequencies lower than 5 GHz. In addition, input return loss (S~11~) lower than −8 dB was achieved for frequencies lower than 4.5 GHz. The chip area is only 0.4 mm^2^, excluding the test pads. This LNA drains 8.75 mA current at supply voltage of 2 V, i.e., it only consumes 17.5 mW power. These results are helpful for RFIC designers to realize miniaturized high‐linearity RF receiver front‐end ICs. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 524–526, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22175