Design and implementation of a high-performance 60-GHz CMOS slot antenna
β Scribed by Chih-Ying Lin; Yo-Sheng Lin; Hsin-Chia Lu; Yi-Long Chang
- Book ID
- 112145080
- Publisher
- John Wiley and Sons
- Year
- 2012
- Tongue
- English
- Weight
- 917 KB
- Volume
- 54
- Category
- Article
- ISSN
- 0895-2477
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Testing is performed by comparison of results from the RBFNN model and the ADS circuit model with the test frequency points (2.41-2.535 GHz, step-size ΒΌ 0.025 GHz), and input powers (Γ9-33 dBm, step-size ΒΌ 1.5 dBm). Figures 4(a) and 4(b) show the AM/AM and AM/PM distortion versus input powers at dif
## Abstract In this article, we demonstrate a miniaturized highβlinearity (IIP3 = 8 dBm at 4 GHz) 3β5βGHz ultrawideband lowβnoise amplifier (LNA) implemented in a standard 0.18βΞΌm CMOS technology. The inductiveβseries peaking technique was used to enhance the gain and bandwidth performances of the