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Design and implementation of a 5×5 trits multiplier in a quasi-adiabatic ternary CMOS logic

✍ Scribed by Mateo, D.; Rubio, A.

Book ID: 119775101
Publisher: IEEE
Year: 1998
Tongue: English
Weight: 170 KB
Volume: 33
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.701275

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