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Design and evaluation of a high throughput robust router for network-on-chip

โœ Scribed by Alhussien, A.; Wang, C.; Bagherzadeh, N.


Book ID
117809938
Publisher
The Institution of Engineering and Technology
Year
2012
Tongue
English
Weight
654 KB
Volume
6
Category
Article
ISSN
1751-8601

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A high level power model for Network-on-
โœ Seung Eun Lee; Nader Bagherzadeh ๐Ÿ“‚ Article ๐Ÿ“… 2009 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 572 KB

This paper presents a high level power estimation methodology for a Network-on-Chip (NoC) router, that is capable of providing cycle accurate power profile to enable power exploration at system level. Our power macro model is based on the number of flits passing through a router as the unit of abstr